In order to fit more circuitry on a semiconductor wafer, semiconductor process engineers are steadily reducing the dimensions of the elements that compose integrated circuits and of the spaces and trenches that separate these elements. These integrated elements may include, for example, transistors and conductive coupling interconnects, such as conductive paths or lines. Such a decrease in the trench dimensions, particularly the trench width, often causes a number of problems. For example, the decrease in trench width may increase the difficulty of filling a trench with a material or of removing the material from the trench. As discussed below in conjunction with FIG. 1, residue or stringers of conductive material that are not removed from a trench may cause short circuits between circuit elements. Such problems and conventional solutions thereto are discussed in U.S. Pat. No. 5,302,233, which is entitled "Method for Shaping Features of a Semiconductor Structure Using Chemical Mechanical Planarization (CMP)," issued on Apr. 12, 1994, and is incorporated by reference herein.
FIG. 1 is a cut away top view of a portion 10 of a semiconductor device, such as a dynamic random access memory (DRAM), having reduced element and trench dimensions. Portion 10 includes three word interconnects or lines 12a-c, which are formed on a substrate 13 and carry signals that fire respective rows of memory cells (not shown) when an external device, such as a processor (not shown), addresses these rows. A field oxide region 14 isolates active substrate areas 16a-b from one another. The word lines 12 are often etched from one or more layers that are formed on the substrate 13 and the field regions 14. Such etching forms trenches 20 between adjacent word lines 12. As shown, the trenches 20 are narrowest where the word lines 12 cross over the field oxide 14. Typically, storage-cell transistors (not shown) are formed in the active areas 16. Plates 18a-b of data storage capacitors associated with active areas 16a-b respectively are formed from a layer of conductive material, such as polysilicon, that is deposited over the word lines 12, field region 14, and active areas 16.
Because the aspect ratios (i.e., depth or height to width ratio) for the trenches 20 are often relatively large, and because the cross-sectional profiles of the trenches 20 are often retrograde, it is often difficult to remove material that has been deposited within the trenches 20. A retrograde, i.e., "bottle neck", cross-sectional profile occurs when the width of the opening to the trench 20 is smaller than the width of the trench 20 beneath the opening. The residue of the conductive material within a trench 20 may form a short circuit, i.e., stringer 22, between two or more capacitor plates 18, and render defective each of the memory cells associated with a respective one of the shorted plates 18. For example, the stringer 22, if present, may render defective both of the memory cells associated with capacitor plates 18a and 18b, respectively.
One technique for removing the conductive material from the trenches 20, and thus reducing or eliminating the formation of the stringers 22, is overetching the layer of conductive material during the formation of plates 18. Such overetching, however, typically reduces the area of plates 18, and thus reduces the storage capacity of the storage capacitors.